SPAF: A System-level Power Analysis Framework

Accurate and efficient power analysis capability at the system-level is an essential ingredient for developing a successful SoC or processor design methodology. Our work presents a \textbf{system-level power analysis} framework that facilitates architectural exploration through a quick and sufficiently accurate power estimation capability. Developing a power analysis framework at systemlevel requires creating an infrastructure to support power estimation and optimization without either one becoming a bottleneck. Currently, designers leverage simulation-driven power estimation techniques that exist at RTL and tolerate the inherent large turn-around time. We developed a power analysis framework called SPAF that reuses RTL power estimation techniques with system-level inputs to avoid these problems. Our solution integrates (i) SystemC and ESTEREL for systemlevel modeling, (ii) Esterel Studio for high-level-synthesis, and (iii) PowerTheater for the RTL power analysis. SPAF is used to quickly and correctly analyze the power consumption of cycle-accurate transaction-level designs that are specified in SystemC. We demonstrate up to 12X speedup in the power analysis time w.r.t an RTL technique with at most 8.7\% loss in accuracy. SPAF: A System-level Power Analysis Framework Sumit Ahuja, Deepak A. Mathaikutty, Gaurav Singh, Sandeep K. Shukla and Ajit Dingankar {sahuja, mathaikutty, gasingh, shukla}@vt.edu and [email protected] 1